Корпуса QFP, LQFP, TQFP. Чертежи корпусов импортных микросхем.
QFP28
QFP32
QFP44
QFP48
QFP64
QFP68
QFP80
QFP100
QFP120
QFP124
QFP144
QFP160
QFP164
QFP176
QFP196
QFP208
TQFP64
TQFP80
TQFP100
TQFP120
TQFP168
LQFP32
LQFP48
LQFP64
LQFP80
LQFP100
LQFP120
LQFP144
Все типы корпусов импортных микросхемПечатать
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NXP Semiconductors. LQFP144 Даташит, LQFP144 PDF, даташитов
General description
The LPC1850/30/20/10 are ARM Cortex-M3 based microcontrollers for embedded applications. The ARM Cortex-M3 is a next generation core that offers system enhancements such as low power consumption, enhanced debug features, and a high level of support block integration.
The LPC1850/30/20/10 operate at CPU frequencies of up to 180 MHz. The ARM Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals. The ARM Cortex-M3 CPU also includes an internal prefetch unit that supports speculative branching.
The LPC1850/30/20/10 include up to 200 kB of on-chip SRAM, a quad SPI Flash Interface (SPIFI), a State Configurable Timer (SCT) subsystem, two High-speed USB controllers, Ethernet, LCD, an external memory controller, and multiple digital and analog peripherals.
Features and benefits
■ Processor core
◆ ARM Cortex-M3 processor, running at frequencies of up to 180 MHz.
◆ ARM Cortex-M3 built-in Memory Protection Unit (MPU) supporting eight regions.
◆ ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).
◆ Non-maskable Interrupt (NMI) input.
◆ JTAG and Serial Wire Debug, serial trace, eight breakpoints, and four watch points.
◆ Enhanced Trace Module (ETM) and Enhanced Trace Buffer (ETB) support.
◆ System tick timer.
■ On-chip memory
◆ 200 kB SRAM for code and data use.
◆ Multiple SRAM blocks with separate bus access.
◆ 64 kB ROM containing boot code and on-chip software drivers.
◆ 32-bit One-Time Programmable (OTP) memory for general-purpose use.
■ Clock generation unit
◆ Crystal oscillator with an operating range of 1 MHz to 25 MHz.
◆ 12 MHz internal RC oscillator trimmed to 1 % accuracy over temperature and
voltage.
◆ Ultra-low power RTC crystal oscillator.
◆ Three PLLs allow CPU operation up to the maximum CPU rate without the need for
a high-frequency crystal. The second PLL is dedicated to the High-speed USB, the
third PLL can be used as audio PLL.
◆ Clock output.
■ Configurable digital peripherals:
◆ State Configurable Timer (SCT) subsystem on AHB.
◆ Global Input Multiplexer Array (GIMA) allows to cross-connect multiple inputs and
outputs to event driven peripherals like timers, SCT, and ADC0/1.
■ Serial interfaces:
◆ Quad SPI Flash Interface (SPIFI) with 1-, 2-, or 4-bit data at rates of up to
52 MB per second.
◆ 10/100T Ethernet MAC with RMII and MII interfaces and DMA support for high
throughput at low CPU load. Support for IEEE 1588 time stamping/advanced time
stamping (IEEE 1588-2008 v2).
◆ One High-speed USB 2.0 Host/Device/OTG interface with DMA support and
on-chip high-speed PHY (USB0).
◆ One High-speed USB 2.0 Host/Device interface with DMA support, on-chip
full-speed PHY and ULPI interface to an external high-speed PHY (USB1).
◆ USB interface electrical test software included in ROM USB stack.
◆ Four 550 UARTs with DMA support: one UART with full modem interface; one
UART with IrDA interface; three USARTs support UART synchronous mode and a
smart card interface conforming to ISO7816 specification.
◆ Up to two C_CAN 2.0B controllers with one channel each. Use of C_CAN controller
excludes operation of all other peripherals connected to the same bus bridge See
Figure 1 and Ref. 1.
◆ Two SSP controllers with FIFO and multi-protocol support. Both SSPs with DMA
support.
◆ One Fast-mode Plus I2C-bus interface with monitor mode and with open-drain I/O
pins conforming to the full I2C-bus specification. Supports data rates of up to
1 Mbit/s.
◆ One standard I2C-bus interface with monitor mode and standard I/O pins.
◆ Two I2S interfaces with DMA support, each with one input and one output. (Continue …)
ru.datasheetbank.com
NXP Semiconductors. LQFP144 Даташит, LQFP144 PDF, даташитов
General description
The LPC1850/30/20/10 are ARM Cortex-M3 based microcontrollers for embedded applications. The ARM Cortex-M3 is a next generation core that offers system enhancements such as low power consumption, enhanced debug features, and a high level of support block integration.
The LPC1850/30/20/10 operate at CPU frequencies of up to 180 MHz. The ARM Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals. The ARM Cortex-M3 CPU also includes an internal prefetch unit that supports speculative branching.
The LPC1850/30/20/10 include up to 200 kB of on-chip SRAM, a quad SPI Flash Interface (SPIFI), a State Configurable Timer (SCT) subsystem, two High-speed USB controllers, Ethernet, LCD, an external memory controller, and multiple digital and analog peripherals.
Features and benefits
■ Processor core
◆ ARM Cortex-M3 processor, running at frequencies of up to 180 MHz.
◆ ARM Cortex-M3 built-in Memory Protection Unit (MPU) supporting eight regions.
◆ ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).
◆ Non-maskable Interrupt (NMI) input.
◆ JTAG and Serial Wire Debug, serial trace, eight breakpoints, and four watch points.
◆ Enhanced Trace Module (ETM) and Enhanced Trace Buffer (ETB) support.
◆ System tick timer.
■ On-chip memory
◆ 200 kB SRAM for code and data use.
◆ Multiple SRAM blocks with separate bus access.
◆ 64 kB ROM containing boot code and on-chip software drivers.
◆ 32-bit One-Time Programmable (OTP) memory for general-purpose use.
■ Clock generation unit
◆ Crystal oscillator with an operating range of 1 MHz to 25 MHz.
◆ 12 MHz internal RC oscillator trimmed to 1 % accuracy over temperature and
voltage.
◆ Ultra-low power RTC crystal oscillator.
◆ Three PLLs allow CPU operation up to the maximum CPU rate without the need for
a high-frequency crystal. The second PLL is dedicated to the High-speed USB, the
third PLL can be used as audio PLL.
◆ Clock output.
■ Configurable digital peripherals:
◆ State Configurable Timer (SCT) subsystem on AHB.
◆ Global Input Multiplexer Array (GIMA) allows to cross-connect multiple inputs and
outputs to event driven peripherals like timers, SCT, and ADC0/1.
■ Serial interfaces:
◆ Quad SPI Flash Interface (SPIFI) with 1-, 2-, or 4-bit data at rates of up to
52 MB per second.
◆ 10/100T Ethernet MAC with RMII and MII interfaces and DMA support for high
throughput at low CPU load. Support for IEEE 1588 time stamping/advanced time
stamping (IEEE 1588-2008 v2).
◆ One High-speed USB 2.0 Host/Device/OTG interface with DMA support and
on-chip high-speed PHY (USB0).
◆ One High-speed USB 2.0 Host/Device interface with DMA support, on-chip
full-speed PHY and ULPI interface to an external high-speed PHY (USB1).
◆ USB interface electrical test software included in ROM USB stack.
◆ Four 550 UARTs with DMA support: one UART with full modem interface; one
UART with IrDA interface; three USARTs support UART synchronous mode and a
smart card interface conforming to ISO7816 specification.
◆ Up to two C_CAN 2.0B controllers with one channel each. Use of C_CAN controller
excludes operation of all other peripherals connected to the same bus bridge See
Figure 1 and Ref. 1.
◆ Two SSP controllers with FIFO and multi-protocol support. Both SSPs with DMA
support.
◆ One Fast-mode Plus I2C-bus interface with monitor mode and with open-drain I/O
pins conforming to the full I2C-bus specification. Supports data rates of up to
1 Mbit/s.
◆ One standard I2C-bus interface with monitor mode and standard I/O pins.
◆ Two I2S interfaces with DMA support, each with one input and one output. (Continue …)
ru.datasheetbank.com
Корпуса микросхем типа QFP, TQFP и LQFP | Электронные компоненты
Корпуса микросхем QFP, TQFP, LQFP\Step AP214\Корпус LQFP-100 (0.50 мм).STEP
Корпуса микросхем QFP, TQFP, LQFP\Step AP214\Корпус LQFP-120 (0.40 мм).STEP
Корпуса микросхем QFP, TQFP, LQFP\Step AP214\Корпус LQFP-144 (0.50 мм).STEP
Корпуса микросхем QFP, TQFP, LQFP\Step AP214\Корпус LQFP-32 (0.80 мм).STEP
Корпуса микросхем QFP, TQFP, LQFP\Step AP214\Корпус LQFP-48 (0.50 мм).STEP
Корпуса микросхем QFP, TQFP, LQFP\Step AP214\Корпус LQFP-64 (0.50 мм).STEP
Корпуса микросхем QFP, TQFP, LQFP\Step AP214\Корпус LQFP-80 (0.50 мм).STEP
Корпуса микросхем QFP, TQFP, LQFP\Step AP214\Корпус QFP-100 (0.65 мм).STEP
Корпуса микросхем QFP, TQFP, LQFP\Step AP214\Корпус QFP-120 (0.80 мм).STEP
Корпуса микросхем QFP, TQFP, LQFP\Step AP214\Корпус QFP-144 (0.65 мм).STEP
Корпуса микросхем QFP, TQFP, LQFP\Step AP214\Корпус QFP-160 (0.65 мм).STEP
Корпуса микросхем QFP, TQFP, LQFP\Step AP214\Корпус QFP-176 (0.50 мм).STEP
Корпуса микросхем QFP, TQFP, LQFP\Step AP214\Корпус QFP-196 (0.65 мм).STEP
Корпуса микросхем QFP, TQFP, LQFP\Step AP214\Корпус QFP-208 (0.50 мм).STEPКорпуса микросхем QFP, TQFP, LQFP\Step AP214\Корпус QFP-44 (1.00 мм).STEP
Корпуса микросхем QFP, TQFP, LQFP\Step AP214\Корпус QFP-48 (0.80 мм).STEP
Корпуса микросхем QFP, TQFP, LQFP\Step AP214\Корпус QFP-64 (1.00 мм).STEP
Корпуса микросхем QFP, TQFP, LQFP\Step AP214\Корпус QFP-80 (0.80 мм).STEP
Корпуса микросхем QFP, TQFP, LQFP\Step AP214\Корпус TQFP-100 (0.50 мм).STEP
Корпуса микросхем QFP, TQFP, LQFP\Step AP214\Корпус TQFP-120 (0.40 мм).STEP
Корпуса микросхем QFP, TQFP, LQFP\Step AP214\Корпус TQFP-168 (0.30 мм).STEP
Корпуса микросхем QFP, TQFP, LQFP\Step AP214\Корпус TQFP-64 (0.50 мм).STEP
Корпуса микросхем QFP, TQFP, LQFP\Step AP214\Корпус TQFP-80 (0.50 мм).STEP
Корпуса микросхем QFP, TQFP, LQFP\Корпус QFP, LQFP, TQFP.SLDPRT
Корпуса микросхем QFP, TQFP, LQFP\Step AP214
Корпуса микросхем QFP, TQFP, LQFP
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